1. Field of the Invention
The present invention relates to a semiconductor memory device and method of manufacturing the same, and more particularly, to a static random access memory cell capable of enhancing the cell ratio and method of manufacturing the same.
2. Description of the Related Art
A semiconductor memory device is classified into a dynamic random access memory (DRAM) and a static random access memory (SRAM) according to its memorizing method SRAM is particularly significant due to its high speed, low power consumption, and simple operation. In addition, unlike the DRAM, the SRAM has advantages of straight forward design as well as not having to regularly refresh stored data.
In general, SRAM cell includes: two driving transistors which are the pull-down devices; two access devices; and two pull-up devices. The SRAM cell is further classified as a full CMOS cell, a high road resistor (HRL), or thin film transistor (TFT) cell according to the type of the pull-up devices used.
The full CMOS cell utilizes a P-channel bulk MOSFET as the pull-up device. The HRL cell utilizes a polysilicon having a high resistance value as the pull-up device, and The TFT cell utilizes P-channel polysilicon TFT as the pull-up device. Of the above-mentioned structures, the SRAM cell with the full CMOS cell structure has optimal operational device properties and can be fabricated with a simple process. It, however, has both NMOS and PMOS transistors in the unit cell, resulting in a large cell size. Therefore, it is applied to memory devices having a small capacitance. On the other hand, SRAM cells with the HRL cell and the TFT cell structures have relatively poor performance and is complicated in their fabrication. Because of their small cell size, however they are generally applied to semiconductor memory devices in cases of larger capacitance.
FIG. 1 is a conventional circuit diagram of an SRAM cell with full CMOS cell structure.
As shown in this diagram sources of PMOS transistors Q1 and Q2 for use in pull-up devices are connected to VDD. Drains of the PMOS transistors Q1 and Q2 are respectively connected in series to drains of NMOS transistors Q3 and Q4 for use in pull-down devices at cell nodes N1 and N2. Sources of the NMOS transistors Q3 and Q4 are connected to VSS. Gates of the PMOS transistors Q1 and Q2 are respectively connected to gates of the NMOS transistors Q3 and Q4, and these connection points thereof are respectively cross-coupled with the cell nodes N1, N2. In NMOS transistors Q5 and Q6 for use in access devices, gates are connected to a word line W/L, sources are respectively connected to bit lines B/L1 and B/L2. Drains of NMOS transistors Q5 and Q6 are respectively connected to the drains of the NMOS transistors Q3 and Q4 at the cell nodes N1, N2.
In the above described SRAM cell, the NMOS transistors Q5 and Q6 are turned on by turning on the word line W/L, to store data in a HIGH state in the node N1 and data in a LOW state in the node N2. Data in a HIGH state is inputted to the bit line B/L1 and data in a LOW state is inputted to the bit line B/L2, so that the PMOS transistor Q1 and NMOS transistor Q4 are turned on, and PMOS transistor Q2 and NMOS transistor Q3 are turned off. Therefore, the node N1 becomes a HIGH state and the cell node N2 becomes a LOW state. Furthermore, although the word line W/L is turned off, the cell node N2 is latched to maintain a LOW state and the cell node N1 is maintained at a HIGH state. Accordingly, data is stored in the cell nodes N1 and N2 respectively.
FIG. 2 is a plan view of the SRAM cell illustrated in FIG. 1. Referring to FIG. 2 with cross reference to FIG. 1, A1 and A2 are the active regions of the PMOS transistors Q1 and Q2 for use in pull-up devices, B1 and B2 are the active regions of the NMOS transistors Q3 and Q4 for use in pull-down devices and the NMOS transistors Q5 and Q6 for use in access devices. C1 to C6 are the contact regions. Here, C1 and C2 denote contact regions of cell nodes N1 and N2. C3 and C4 denote contact regions of sources the NMOS transistors Q5 and Q6. C5 denotes contact regions of sources of the PMOS transistors Q1 and Q2, and C6 denotes contact regions of sources of the NMOS transistors Q3 and Q4. There are also provided word lines 34a, 34b, and 54.
Meanwhile, FIG. 3 is sectional view of the active region B1 taken along line III-III' of FIG. 2, and illustrates the sectional structure of the NMOS transistor Q3 for use in pull-down devices and the NMOS transistor Q5 for use in access devices.
As illustrated in FIG. 3, the NMOS transistor Q3 for use in pull-down devices and the NMOS transistor Q5 for use in access devices include: a semiconductor substrate 1 having an active region B1 of the NMOS transistor Q3 for use in pull-down devices and the NMOS transistor Q5 for use in access devices defined by a field oxide layer 2; a gate oxide layer 3 formed on the substrate 1 between the field oxide layer 2 and gates 34a and 54; source regions 5a, 5c and a common drain region 5b formed in the active region B1 both sides of the gates 34a and 54; an intermediate insulating layer 6 formed on the overall surface of the substrate and having a contact hole which expose predetermined portions of the source regions 5a, 5c and the drain region 5b; metal-interconnection layers 7a, 7b and 7c connected with the source regions 5a, 5c and the drain region 5b through the contact holes.
Meanwhile, one of the factors determining the characteristics of the SRAM is the current driving capability ratio of the pull-down device, otherwise known as the driving device and the access device (I.sub.DSAT DRIVER TRANSISTOR /I.sub.DSAT ACCESS TRANSISTOR), otherwise known as cell ratio. A higher cell ratio results in improved performance of the SRAM. Therefore when the current amount of the pull-down device is large and the current amount access device is small, the performance of the SRAM cell is improved.
An operation of the SRAM related to the cell ratio is as follows. In case that the data in a low state is stored in the node N1 and the data in a high state is stored in the cell node N2, the voltage of the cell node N1 is determined by the current amount ratio of the NMOS transistors Q5 and Q6 for use in access devices and the NMOS transistors Q3 and Q4 for use in pull down devices. Accordingly, the node N1 is intended to maintain the low voltage with the increase of the current amount of the NMOS transistors Q3 and Q4, and with the decrease of the current amount of the NMOS transistors Q5 and Q6. If so, the voltage of the cell node N1 is not drastically changed from the low state when the NMOS transistors Q5 and Q6 are turned on during the reading operation, even though the voltage of the bit line B/L1 is changed. In case the voltage variation of the cell node N1 is small, the voltage of the cross-coupled the cell node N2 is still maintained in the high state.
Therefore, conventionally, the cell ratio is controlled in a manner wherein width of the NMOS transistor for use in access devices is reduced and its length is increased thereby increasing its the current amount, and width of the NMOS transistor for use in pull-down devices is increased and its length is reduced to thereby reduce its the current amount. The width and length of the transistor, however, cannot be reduced below a predetermined level, and therefore there is a restriction in reducing the size of the cell to enhance the cell ratio.